The document DE 196 35 582 C1 discloses a power semiconductor component for bridge circuits having so-called high-side switches or low-side switches, which component has a first base power semiconductor chip containing a vertical first transistor. A further, second power semiconductor chip having a second vertical transistor is mounted on the first base power semiconductor chip, so that the conduction paths of the two transistors are connected in series via the surface-mounted large-area contacts. An arrangement of this type can be extended in a simple manner to form a full bridge, as shown in FIGS. 6 and 7.
FIG. 6 shows the bridge circuit 616 of power semiconductor chips which is known from the prior art, the base power semiconductor chip 61 being mounted on a so-called cooling area 66 and containing two semiconductor switches H1, H2 which are insulated from one another on the source side. The two drain connections of the semiconductor switches H1 and H2 form the rear side of the base power semiconductor chip 61, said rear side being mounted on the cooling area 66. Two further power semiconductor chips 62 and 63 are then stacked on the source areas of the two transistors H1 and H2, said source areas being situated on the top side of the base power semiconductor chip 61.
These stacked power semiconductor chips 62 and 63 respectively have further power transistors L1 and L2. In this respect, the drain regions of the transistors L1 and L2 are mounted on the respective source region of the power transistors H1 and H2 and form the nodes 64 and 65 which can be connected via the respective external connections 610 and 614. The respective source regions of the power transistors L1 and L2 can likewise be contact-connected via the external connections 67 and 68 by bonding. The external connections 69, 611, 613 and 615 serve for driving the respective transistors H1, H2, L1 and L2 of the full bridge 616.
One realization of the bridge circuit 616 is shown in FIG. 7, in which the bridge circuit 616 is arranged in a surface-mountable housing 720 with external connections 722. In this case, the two source areas of the transistors H1 and H2 situated on the surface of the base power semiconductor device 61 are larger than the second and third stacked power semiconductor chips 62 and 63 mounted on them. As a result, contact can be made by the contact-making areas at the nodes 64 and 65 in a simple manner by means of bonding wires 724 and 726 with the external connections 722. The source areas of the semiconductor chips 62 and 63 are also likewise connected to respective externally accessible connections 722 from above by means of bonding wires 723 and 725.
This arrangement has the disadvantage that the drain connection basic areas of the low-side switches L1 and L2 contained in the power semiconductor chips 62 and 63 are dependent on the size of the respective source contact-making areas of the high-side switches H1 and H2 in the base power semiconductor chip 61. The base power semiconductor chip 61 thus does not permit any great variation possibilities as regards its large-area external contacts since the power semiconductor chips to be stacked are always surface-mounted in the prior art via the respective large-area external contacts present. The permissible current consumption of the bridge circuit branches is also significantly restricted by the limited size of the stacked power semiconductor components 62 and 63.